This invention relates to means for ascertaining the fabrication tolerances of integrated circuit (IC) assemblies, particularly Very Large Scale Integration (VLSI) devices. One or more test structures are included on a silicon wafer at the various stages of its manufacture as described in Aton et al., U.S. Pat. No. 5,361,137. These test structures are not necessarily designed to be electrically functional IC's but rather sampling areas on the wafer from which the fabrication tolerances of the IC manufacturing process can be tested. This invention particularly lends itself to real-time, non-contact, and in-process determination of such accuracy.
The typical process for the manufacture of ICs is well known and consists of the sequential deposition, and partial removal by etching, of conducting and insulating materials. As the demand for computer performance has exponentially increased over the years the manufacturing tolerances used in making ICs have tightened considerably. Typical manufacturing processes now have to deal with device and interconnect geometries whose minimum characteristic dimensions are rapidly approaching 0.1 microns and are therefore beyond the resolving power of traditional optical microscopes.
Various efforts have been made to gauge (measure) those increasingly narrowing manufacturing tolerances. One approach is found in Kleinknecht U.S. Pat. No. 4,408,884 and references cited therein which describe the use of a monochromatic light source, such as a laser beam, focused on a test portion of silicon wafers. The portion of the beam diffracted off the pattern (diffraction grating pattern) on the wafer is carefully measured to determine the accuracy and reliability of the manufacturing process.
One disadvantage of the approach in Kleinknecht U.S. Pat. No. 4,408,884 is the difficulty and time needed to analyze the complex patterns generated by the laser beam as it diffracts off the test grating patterns. The approach of the Kleinknecht patent is therefore highly impractical as an in-process (real-time) method of analyzing chip production tolerances.
One proposal for a real-time method of measuring submicron line widths during chip manufacture is described in Aton U.S. Pat. No. 5,361,137. That patent describes a method of measuring the first and second order intensities of diffraction peaks from test areas containing test gratings of known spacing or pitch. However, this technique suffers from the same problems of analysis as that of Kleinknecht et al., since relatively simple test gratings are employed to produce highly complex diffraction patterns.
This invention solves the problems with these approaches and provides a practical real-time analysis of dielectric thickness, planar uniformity, edge roughness, mask alignment, and other chip manufacturing process parameters.